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this post was submitted on 10 Aug 2025
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This isn't completely true. Even a basic instruction like ADD has multiple implementations depending on the memory sources.
For example, if the memory operand is in RAM, then the ADD needs to be decoded to include a fetch before the actual addition. RISC doesn't change that fact.
Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn't help with data cache.
Are you sure there's a significant difference in machine code between RISC and CISC after instructions are decoded?
The assembly in RISC is just an abstraction of the machine code, as it also is in CISC. If the underlying CPU has the same capabilities then it doesn't really matter what the assembly looks like?
Of course, the underlying CPUs aren't the same and that's the real point of differentiation.
See my other reply